|
Twitter
|
Facebook
|
Google+
|
VKontakte
|
LinkedIn
|
Viadeo
|
English
|
Français
|
Español
|
العربية
|
 
International Journal of Innovation and Applied Studies
ISSN: 2028-9324     CODEN: IJIABO     OCLC Number: 828807274     ZDB-ID: 2703985-7
 
 
Monday 20 May 2019

About IJIAS

News

Submission

Downloads

Archives

Custom Search

Contact

Connect with IJIAS

  Now IJIAS is indexed in EBSCO, ResearchGate, ProQuest, Chemical Abstracts Service, Index Copernicus, IET Inspec Direct, Ulrichs Web, Google Scholar, CAS Abstracts, J-Gate, UDL Library, CiteSeerX, WorldCat, Scirus, Research Bible and getCited, etc.  
 
 
 

Design and Implementation of Efficient Elevator Control System using FPGA


Volume 9, Issue 4, December 2014, Pages 1541–1546

 Design and Implementation of Efficient Elevator Control System using FPGA

Muhammad Ahsan Ullah1 and M. A. Saeed2

1 Electronic Engineering Department, Islamia University, Bahawalpur, Pakistan
2 Faculty of Electrical Engineering, GIK Institute, Topi, Pakistan

Original language: English

Received 30 October 2014

Copyright © 2014 ISSR Journals. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract


Many industrial and control applications are running through conventional PLC technology adequately because PLC provides flexibility, lower cost and security compared to other control techniques, but still a more powerful alternative is needed. In recent years, FPGA's becomes the best replacement of PLC to implement control algorithms in industrial, digital signal processing, video and audio applications and as well to perform control tasks. The basic dilemma of FPGA's is that it requires an expertise in control automation applications. In this paper, an efficient methodology is proposed to implement PLC state diagram on FPGA using Xilinx StateCAD tool. Three level efficient elevator control system is designed which can be used for different elevator control system having different number of floors. Simply changing the state diagram, VERILOG HDL(Hardware Description Language) code is generated and used in XILINX ISE 7.1i to implement control system on FPGA Spartan-3. StateBench simulator is used to simulate results of proposed control system.

Author Keywords: Programmable Logic Controller, Field Programmable Gate Array, State Diagram, StateCAD, Hardware Description Language.


How to Cite this Article


Muhammad Ahsan Ullah and M. A. Saeed, “Design and Implementation of Efficient Elevator Control System using FPGA,” International Journal of Innovation and Applied Studies, vol. 9, no. 4, pp. 1541–1546, December 2014.